CAD STA Technologist
Apple
- Sunnyvale, CA
- Permanent
- Full-time
- STA timing closure experience of gate level and transistor level designs in advanced CMOS process.
- Thorough understanding of STA and methodologies for timing closure, good understanding of noise, cross-talk, OCV effects, and the ability to understand the relationship between those methodologies to provide waiver for ECO violations.
- Excellent data analytical, problem solving, and communication skills.
- Experience working with cross-functional teams and driving decision making is highly desired.
- Understanding of front end timing methodologies and constraints as they relate to backend analysis closure and PPA (power, performance, area) target optimization.
- Programming experience in Python required.
- Prior experience delivering new designs to production under a very ambitious schedule ideal.
- Knowledge of PrimeTime & NanoTime setup/flow automation, Spice simulation and understanding of derates and margins in typical STA/glitch noise closure a bonus.
- Self-motivated and schedule oriented is a big plus.