Senior R&D engineer (FPGA Developer) @ Hitachi Energy
Hitachi Energy
- Kraków, małopolskie
- Stała
- Pełny etat
- At least Master's degree in Electronics/Control Engineering or related field. Experience of FPGA/ASIC design & simulation in VHDL/(and/or Verilog) - 5 years for Senior, 5-10 for Senior II
- Good understanding of synchronous design, time constraining and static timing analysis.
- Experience with laboratory equipment, prototyping and testing.
- Strong commitment to safe work practices and dedication to following all relevant workplace safety guidelines.
- High level of self-motivation, curiosity, and desire to learn about modern technologies.
- A collaborative, solutions-oriented approach, and effective communication skills.
- Experience in modelling in High Level Synthesis would be an advantage.
- Experience in self-testing test-benches and regression tests would be an advantage.
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