Engineering, Sr Staff Engineer
Synopsys
- Austin, TX
- Permanent
- Full-time
- Design verifications for digital sensor IP's in development.
- DV at RTL/Gate level; DV coverage analysis; coverage improvements.
- Engage in gate level simulations; flow automation scripting; test plans.
- Work with IP design engineers to fully enable new IP's.
- Capability contributing to design arch a plus.
- Languages: Verilog, SV.
- Methodologies: UVM.
- Scripting: makefile/Python.
- Involved in IP/SOC level verification.
- Developed and maintained IP level UVM/SV environments.
- Exposed to SV assertion-based verification.
- Test planning and coverage closure.
- Knowledge of Bus protocols like AXI, AHB, APB, JTAG.
- Gate level Simulation experience.
- Experience of developing SOC environments and C based testcases.
- 5+ years of industry experience is highly desirable.
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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
“The base salary range across the U.S. for this role is between $93,000-$162,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon requestHire TypeEmployeeJob CategoryEngineeringJob SubcategoryEngineeringBase Salary Range135000-203000