ASIC Digital Design, Staff Engineer
Synopsys
- Kanata, ON Nepean, ON
- Permanent
- Full-time
- BSEE degree or Applied Science degree (or equivalent) with 5+ years of related experience as well as experience in verifying designs at the chip level and block level.
- Strong Verilog and SystemVerilog skills are required as well as in-depth knowledge of the UVM methodology.
- Candidates will have knowledge of System Verilog Assertions and/or assertion based verification. Knowledge of IP development and/or the DDR memory protocol are valuable assets as are scripting languages such as Python, PERL and TCL.
- Candidates will have experience with back-annotated gate level simulations at the chip level and block level.
- Excellent communication and presentation skills
- Well organized, methodical, detail oriented and possess knowledge in product debugging.
- Previous knowledge in customer support is an asset.
#LI-JW4Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryASIC Digital Design