ASIC Digital Design, Sr Staff Engineer

Synopsys

新竹市
長期
全職

16天前

Job Description and RequirementsOur Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.Sr Staff Digital IP Verification EngineerSeeking a highly motivated and innovative Staff digital IP verification engineer with knowledge of DDR and wide-spectrum knowledge of generic IP verification methodology.The candidate would be working as part of a highly experienced DDR controller design and verification team, targeting the current and next generation DDR technology, such as DDR5, LPDDR6. Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus.The position offers an excellent opportunity to work with a professional team of digital engineers responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases.The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.Does this sound like a good role for you?Responsibility and Key Qualification

This position is for leading edge IP verification.
Study standard specifications published by JEDEC.
Work on and further develop UVM methodology-based verification platform.
Study design micro architecture, implement high quality verification from defining verification strategy, plan and implement infrastructure, down to analyze and debug regression failures, and reach full function coverage.
Work with design team to debug and fix RTL issues.
Work with VIP teams for VIP issues
Must be self-motivated, proactive, and able to achieve good quality while meeting tight deadlines.
Guide team members with aspects of their job. Networks with senior internal and external personnel in own area of expertise
Good communication skills for interacting between different design groups and customer support teams are required.

Preferred Experience

MSEE plus with a minimum of 8 years of experience in UVM-based verification methodology. And demonstrates good analysis and problem-solving skills.
Knowledgeable and experienced in UVM, assertions. Skills in Formal verification is a plus.
Knowledgeable in DDR. Knowledge in AMBA protocols is a plus.
Scripting experience in Shell, Perl, Python and TCL is a plus.
Be fluent in English, both speaking and writing.
Has strong desire to learn and explore new technologies.
Demonstrates good attitude in teamwork.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryASIC Digital Design

Synopsys

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