Cellular ASIC Design Integration Engineer
Apple
- Irvine, CA
- Permanent
- Full-time
- This position requires thorough knowledge of the ASIC design flow, FE and design verification, synthesis, scripting, and netlist generation.
- Knowledge of ASIC/SoC design flow.
- Knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX) and Synthesis and STA flows.
- Strong knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.)
- Strong analytical skills to be able to make design tradeoffs for best performance, low area, and low power.
- Experience in driving power improvements based on power analysis tools/flows.
- UPF flow for defining the power intent of chips with multiple power domains.
- Experience in writing efficient design synthesis and STA constraints.
- Work with the DV team to come up with a thorough verification plan and drive coverage closure.
- Design interfacing with PD for floor planning and timing closure.
- Experience with version control tools and handoff of design releases.
- Strong scripting skills to automate tasks and build scalable design flows.
- Self-starter, highly motivated, highly organized, and schedule-driven, which is a must.
- Familiarity with DFT, MBIST, and backend-related methodologies and tools is a plus.