Senior E/E & Semiconductor Engineer - Design Verification Engineer
Capgemini
- Santa Clara, CA
- $88,800-187,740 per year
- Permanent
- Full-time
- Flexible work
- Healthcare including dental, vision, mental health, and well-being programs
- Financial well-being programs such as 401(k) and Employee Share Ownership Plan
- Paid time off and paid holidays
- Paid parental leave
- Family building benefits like adoption assistance, surrogacy, and cryopreservation
- Social well-being benefits like subsidized back-up child/elder care and tutoring
- Mentoring, coaching and learning programs
- Employee Resource Groups
- Disaster Relief
- IP verification is coverage driven using the latest industry standard methodologies and HVLs.
- Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
- Code coverage, Functional coverage and assertions are desired.
- ARM based SoC verification experience is an added advantage.
- Design Verification background, but more focused or specialized in the python scripting, tool implementation using python
- Experience with SV+UVM/OVM/VMM
- Independently contribute to verification environment development.
- Prior experience with assertions, functional coverage & code coverage is desired.
- Experience with SOC with C/ASM based tests, Graphics or CPU is an advantage
- Proficient on protocols – AXI, AHB, USB, PCIe, DDR, LPDDR, HDMI, MIPI, ethernet.
- SV+UVM, Python, C/C++