Senior E/E & Semiconductor Engineer - Meta_Design Verification Engineer
Capgemini
- Santa Clara, CA
- Permanent
- Full-time
- Flexible work
- Healthcare including dental, vision, mental health, and well-being programs
- Financial well-being programs such as 401(k) and Employee Share Ownership Plan
- Paid time off and paid holidays
- Paid parental leave
- Family building benefits like adoption assistance, surrogacy, and cryopreservation
- Social well-being benefits like subsidized back-up child/elder care and tutoring
- Mentoring, coaching and learning programs
- Employee Resource Groups
- Disaster Relief
- ~ 10 years of experience in UVM based verification
- System Verilog assertions experience
- Familiarity with C/C++ model integration in verification environments
- Debug skills at IP and subsystem level
- GLS verification knowledge
- Low power – UPF – verification
- ARM based SoC level verification experience