Design Verification, Staff Engineer
Marvell
- Tp Hồ Chí Minh
- Lâu dài
- Toàn thời gian
- Define verification-plan/test-plan/coverage-plan
- Define/develop testbench based on the latest advanced Verification methodologies using Verilog/System-Verilog/UVM, System-C/C/C++, etc.
- Define/implement tests to verify RTL-designs according to verification/test plans defined
- Implement code coverage, functional coverage.
- Implement Gate Level Simulation
- Be responsible for verification sign-off of various chips, make sure that areas of designs that you are responsible for will be released on time with perfect quality
- BS/MS in Electrical, Computer, or Computer Science with high GPA score
- 3-10 years of experience in ASIC verification
- Knowledge of ASIC design and verification flow including RTL design, simulation, synthesis, test bench development, regression
- Knowledge of UNIX environment, Perl, Shell scripting, Verilog/SystemVerilog language
- Good written and oral communication skills in English
- Knowledge of verification methodology such as UVM and/or Formal Verification is a plus
- Knowledge of CPU Subsystem, DDR, PCIe, SAS, SATA is a big plus
- Knowledge of low power design and verification techniques (CPF/UPF, Low Power and Power Aware Simulation, Power estimation,..) is a big plus