Senior Principal Technical Lead - RTL Architecture and Design
Advanced Micro Devices
- Santa Clara, CA
- Permanent
- Full-time
- Technical leadership and technical direction setting for whole memory PHY RTL team.
- Working with customers and consumers to understand feature requirements and translate them into implementable specs
- Definition of RTL architecture, microarchitecture, and design implementation of memory PHYs
- Documentation of RTL architecture and micro-architecture
- RTL coding, code reviews and debug
- Setting and enforcing quality standard for RTL development
- Engagement in Post-Silicon activities such as Bring-Up, Platform Validation, Characterization, Parameters Optimization and final Productization
- Support the definition of development flows that improve efficiency and quality of execution.
- Work closely with Physical Design, Firmware and Design Verification to ensure successful end-to-end RTL implementation.
- A proven record of successful tape-outs and IPs productization, preferrably in high-speed IPs (Memory or Serdes)
- Ability to translate a product feature description into an implementable architecture/design that may include RTL and or Firmware, including clear documentation enabling the implementation and verification of the design.
- Skill and experience in guiding teams at a technical level and working with external groups to understand requirements and devise/negotiate workable solutions to inter-IP challenges.
- Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices.
- Understanding of and experience in refactoring/restructuring designs to solve timing/area challenges. Includes algorithmic and structural design changes.
- Experience and understanding of optimizing hardware vs firmware implementation for overall product performance/efficiency.
- Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL design (front-end and back-end) and Design Verification