Design Verification Engineer job at Folsom, CA
Infobahn Softworld - Santa Clara, CA
Role Title: Design Verification Engineer Location: Folsom, CA Duration: 12+ months contract THE ROLE...: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part...
June 6
Design Verification Staff Engineer
Marvell - Santa Clara, CA - $100,840-151,000 per year
, Ethernet, and ARM CPU cores. What You Can Expect As a SoC-level design verification engineer, the candidate... will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. He...
April 12
Design Verification Engineer, Senior Staff
Marvell - Santa Clara, CA - $124,160-186,000 per year
standard tools and processes Develop constrained-random verification test environment using System Verilog, UVM and C... and other verification engineers to develop and implement verification test plans, schedules, and project deliverables. Manage, debug tests...
May 16
Design Verification Engineer, Principal
Marvell - Santa Clara, CA - $137,510-206,000 per year
testbench components using SystemVerilog, UVM, C, and C++. Create comprehensive test plans based on architecture and design... design blocks. Investigate and debug test failures, identifying root causes related to both the test environment and the...
April 17
Staff Engineer - Design Verification
Marvell - Santa Clara, CA - $100,840-151,000 per year
using System Verilog/UVM/OVM. Strong experience with writing and executing detailed verification test-plan... mechanisms. Strong experience with object-oriented design and implementation. Preferred/Plus: Hands-on verification...
April 12