
Senior Firmware/FPGA Design Engineer
- Rancho Santa Fe, CA
- $104,650-189,175 per year
- Permanent
- Full-time
- Collaborate with a multidisciplinary design team (electrical engineers, systems engineers, and scientists) to implement and integrate FPGA designs and sensor systems.
- Analyze, design, simulate, and implement algorithms in hardware descriptor languages, HDL (VHDL, Verilog), based on MATLAB model(s).
- Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
- Analyze schematic diagrams for either custom or commercial-off-the shelf (COTS) electronic hardware involving high-speed digital and/or analog circuitry in associated FPGA-centric systems.
- Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications for selecting next-generation components for deliverable systems.
- Work on problems of diverse scope, determining methods and procedures to be used on new assignments, and providing feedback and recommendations to other technical personnel.
- Develop project test plans and test procedures, provide test planning support, and assist in the execution of both lab testing and field testing.
- Develop and maintain requirements documents, functional specification documents, interface control documents, etc.
- Bachelor's degree in Electrical or Computer Engineering with 8-12 years of relevant experience.
- Experience with, and understanding of, FPGA system design and test.
- Experience with embedded Software/Firmware design.
- Experience with C/C++, MATLAB.
- Understanding of multiple high-speed serial communication standards and interfaces (e.g. Aurora, 10Ge, PCIe, DDR4/3/2/1, JESD204B)
- Experienced with version control systems including SVN and Git.
- Hands-on laboratory experience with instrumentation, test equipment, and debug/test methods.
- Candidate must be a US Citizen and possess (and be able to maintain) a Final DoD Secret Clearance.
- Familiarity with modern Xilinx FPGA families and design tools (7-series FPGAs, Ultrascale+, Vivado, Xilinx IP cores).
- Experience working with SoC designs such as Zynq and Zynq Ultrascale+ including architecting and interfacing with peripherals, interrupts, and related bus architectures.
- Experience developing and implementing FPGA-optimized versions of DSP algorithms (e.g., modulation/demodulation, PLLs, filters, image processing).
- Experience with standard internal interfaces such as AXI4, AXI4-Stream, and AXI4-Lite.
- Experience working with embedded operating systems (i.e., RTOS such as Green Hills).
- A Masters (MS) degree in Engineering discipline.