System DV Engineer
Micron
- 新竹縣
- 長期
- 全職
- Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
- 5+ years of SoC Design Verification experience using UVM System Verilog methodology.
- System C or C++, scripting skills
- Experience in SoC plus CPU emulation verification environment
- Proven track record of building test plans and coverage closure
- Clear mindset on how to achieve DV quality signoff
- Good communication skills in English and Mandarin to work in a cross-functional team in cross-geographical locations
- B.S. or above in Electrical Engineering or Computer Science related majors