Senior Engineer - RTL Design
Qualcomm
- Noida, Uttar Pradesh
- Permanent
- Full-time
Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Preferred Qualifications:
- Master's degree in Computer Science, Engineering, Information Systems, or related field.
- 3+ years of Hardware Engineering or related work experience.
- 2+ years of experience with circuit design (e.g., digital, analog, RF).
- 2+ years of experience utilizing schematic capture and circuit simulation software.
- 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.
- Experience in Logic design /micro-architecture / RTL coding
- Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs.
- Experience in Verilog/System-Verilog is a must.
- knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
- Work closely with the SoC DFT, Physical Design and STA teams
- Hands on experience in Low power SoC design is required
- Hands on experience in Multi Clock designs, Asynchronous interface is a must.
- Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required.
- Understanding of constraint development and timing closure is a plus.
- Experience in Synthesis / Understanding of timing concepts