Digital Design Engineer (Senior to Senior Staff)
Marvell
- Tân Bình, Tp Hồ Chí Minh
- Lâu dài
- Toàn thời gian
The ODSP team is a key part of Optical and Copper Connectivity Business Unit that drives key design wins for 50G-PAM4, 100G-PAM4, up to 800G-PAM4 DSP products.
At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
We move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions.What You Can Expect
- Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing and noise violations at full chip/block level for SoCs.
- Perform logic synthesis at sub-system or top level for multi-million gate ASIC projects.
- Perform RTL design check: RTL Lint, CDC.
- Work closely with RTL Design engineer and Physical Design engineers on logic synthesis, constraint, timing, power and physical issues.
- Manage schedules and support cross-functional engineering effort.
- Implement, enhance, and maintain Synthesis, STA scripts and various automation flows.
- Contribute to the continuous development of IC design flow.
- BS/MS in Electrical Engineering/Computer Engineering, or related fields and 3-8 years of working experience in VLSI industry.
- Good understanding of ASIC design flow.
- Demonstrate experience and hands-on practical knowledge with Static Timing Analysis (STA) and logic synthesis.
- Hand-on experience with any of constraint management, constraint verification, timing ECO, RTL Lint and Clock Domain Crossing (CDC) Analysis, logic equivalence checking (LEC) and logic ECO.
- Familiar with relevant industry standard EDA tools for logic synthesis (Design Compiler or Genus), STA (PrimeTime or Tempus), LEC (Formality or Conformal).
- Strong automation skills using scripting languages like TCL/PERL/SHELL.
- Demonstrate strong analytical and problem-solving skills through relevant experiences, be a good team player and a dedicated team member.
- Strong written and verbal communication in English.
- 3+ years of Static Timing Analysis experience is a plus.
- Nice to have RTL coding, Design verification experience, DFT and Physical Design experience.
- Knowledge about SERDES, Data Communication, Communication Standards (IEEE, Ethernet protocols) is a plus.