Staff Digital Verification Engineer
Renesas Electronics - Jhubei, Hsinchu County
digital level verification. Modeling of analog functions in SystemVerilog. Responsible for complete chip level verification... of mixed signal IC. Work closely with design team to architect a new design verification environment and produce high quality...
June 1
Staff Digital Verification Engineer
Renesas Electronics - Jhubei, Hsinchu County
infrastructure using SystemVerilog, UVM and Formal. Responsible for complete digital level verification. Modeling of analog... functions in SystemVerilog. Responsible for complete chip level verification of mixed signal IC. Work closely with design team...
May 25
Sr Digital Verification Engineer
Renesas Electronics - Jhubei, Hsinchu County
: Define testbench infrastructure using SystemVerilog, UVM and Formal. Responsible for complete digital level verification.... Modeling of analog functions in SystemVerilog. Responsible for complete chip level verification of mixed signal IC. Work...
June 1
Staff Engineer, Design Verification
Marvell - Hsinchu City - Jhubei, Hsinchu County
Expect IP/SOC/ASIC DV engineer responsible for planning and coordinating the design verification, and evaluation in high...-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog...
April 18
ASIC Digital Design, Sr Staff Engineer
Synopsys - Hsinchu City
, we want to meet you. Sr Staff Digital IP Verification Engineer Seeking a highly motivated and innovative Staff digital IP... verification engineer with knowledge of DDR and wide-spectrum knowledge of generic IP verification methodology. The candidate...
May 14