Senior ASIC Design Verification Engineer
Tarana Wireless
- Milpitas, CA
- $130,000-175,000 per year
- Permanent
- Full-time
- Work with some of the best DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level
- Build and continuously improve verification infrastructure and methodologies to meet the demands of next generation SoCs
- Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project
- Ability to handle complex and hard-do-solve problems in programming and verification
- Ambitious and dedicated
- Good interpersonal skills
- Solid knowledge and strong experience of System Verilog, UVM, and C/C++
- Experience with building abstraction layered and reusable verification testbench infrastructure
- Working knowledge of scripting languages such as Python
- BSEE required/MSEE preferred
- 5-12 years of experience
- Exceptional analytical skills and problem-solving skills
- Proficiency with at least one of these: C++, Object Oriented Programming, UVM, System Verilog
- Strong knowledge on basic concepts of VLSI, SoC architecture
- Ethernet and packet processing experience