Signal and Power Integrity Engineer (Multiple Locations)
- San Diego, CA
- Permanent
- Full-time
ASICS EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!The candidate will work in a team-oriented, professional engineering environment to perform a variety of signal and power integrity tasks and collaborate with package and IC designers to optimize the overall package design, including:
- Utilizing experience and expertise in SRAM, DRAM, DDR, LPDDR, HBM, GDDR and newly emerging memory technologies to drive the SIPI analysis, selection, definition, and implementation of memory system architectures for Data Center products
- Electrical model extraction and signal and power integrity simulations will constitute the majority of the tasks.
- Interfacing with a variety of board, package, and IC designers. Working effectively across organizational boundaries is essential, as is effective documentation and presentation of results.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Responsibilities:
- Engage with customers and product managers to understand product requirements; research and analyze potential memory technologies; engage directly with memory vendors and suppliers to evaluate options and drive requirements; quantify the tradeoffs
- Recommend technical direction with robust justification.
- Effectively communicate and collaboratively engage with the other SoC & IP architects, designers, systems engineers, product managers, and software teams to define Memory System solutions enabling market-leading Data Center products.
- Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include a variety of serial and memory interfaces.
- Apply established methodologies to analyze IO power distribution in product development and reference systems.
- Perform package extraction for time domain and frequency domain SIPI analysis and provide design guidelines for the package design.
- Create clear and complete documentation of results.
- 8+ years of experience with 5+ years in DDR/SerDes in Package/PCB/System Design related to compute/server standards.
- Experience in electromagnetics and a solid background in transmission line theory and crosstalk.
- Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity, and SPICE transient simulation (ADS, Hspice), including use of IBIS and IBIS AMI models.
- Outstanding memory architecture expertise on SRAM, DRAM, DDR, LPDDR, HBM, GDDR and emerging memory technologies such as STT-MRAM, PIM, etc.
- Understanding internal memory technology organization, including DRAM bank & array arrangement, rows and columns, row buffer operation, internal data bus pathways, refresh, power state control, etc.
- Understanding of memory controller architecture, memory scheduling, prioritization and QoS
- Understanding memory PHY parameters and tradeoffs, including for LPDDR, DDR, and HBM
- Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
- Experience working with or working at the major DRAM and other memory vendors
- Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area
- Understanding memory technology parameters such as reliability, thermals, ECC, encryption, etc.
- PHY shoreline, packaging, stacking, etc.
- Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization
- Ability to abstract appropriately to define problems and solution, and make data-drive decisions
- Record of quantitative analysis using (and developing) tools such as high-level calculators & spreadsheets, DRAM timing simulators, profilers, functional and performance simulators, etc.
- Experience driving JEDEC or similar standardization is a plus
- Experience in DDR design specifications such as DDR and LPDDR
- Experience in SerDes design specifications such as PCIe, USB, UFS, and MIPI.
- Experience in Matlab to automate existing simulation flow.
- Experience in programming languages (C/C++) or scripting languages (Perl/Python) is a plus.
- Master’s or Ph.D. degree with 8+ years of industry experience.