Lead Solutions Engineer
Cadence Design Systems
- Bangalore, Karnataka
- Permanent
- Full-time
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
- System Verilog experience and experience with UVM based functional verification environment development is required.
- Good knowledge of verilog/vhdl/C/C++/Perl/Python.
- Expertise in AMBA protocols. (AXI/AHB/APB).
- Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
- Good handle on using one or more version control software
- Good handle on using one or more load sharing software
- Prior experience with Cadence tools and flows is highly desirable.
- Familiarity with ARM/CPU architectures is a plus.
- Experience in developing c-based test cases for SOC verification
- Some experience with assembly language programming
- Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
- Embedded C code development and debug
- Formal Verification experience