Layout Design, Principal Engineer

• Design circuit for Analog IPs like High Speed IOs, PLL, DLL, Bandgap, Clock trees, Calibration circuits... for Die to Die, UCIe, DDR, HBM, Serdes PHY of Synopsys.
• Work closely with layout engineer to make sure layout quality. Perform post layout verifications.
• Design analysis and solve problems of noise, margin, signal integrity, power integrity.
• Complete all design quality checks and data quality checks
• Do design reviews across global team
• Work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.
• Design test chip architecture to test analog designs.
• Build up test cases and run tests in the Synopsys Laboratory to prove design work in silicon.
• May join research programs to implement new ideas for future products and flows.
• May lead a team to develop a completed design.
• Training for junior engineers and interns

Synopsys