ASIC Digital Design, Staff Engineer

Synopsys

上海市
长期
全职

24天前

Job Description and RequirementsOur Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.Digital IP Verification EngineerWe're looking for Digital IP Verification Engineer to join our Shanghai team.
Does this sound like a good role for you?Responsibility:

Create UVM testbenches, tests, and constraints to ensure design correctness
Design, develop, and maintain modular and reusable UVM testbenches for IP verification
Define verification plan based on standard specifications
Create randomized tests, adding constraints and directed tests to fully cover functionality
Confirm test completeness through code and functional coverage
Review testbenches, tests, and coverage with designers, architects
Integrate tests and coverage within full environment

Qualification:Be familiar with SystemVerilog and UVMTypically requires a minimum of 5 years of IP Verification experienceUnderstanding in any high performance interface technologies, e.g. DDR, PCIe, ethernet, is a plusBe fluent in English, both speaking and writingHas solid desire to learn and explore new technologiesDemonstrates good attitude in team workInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryASIC Digital Design

Synopsys

立即申请