Design Verification Staff Engineer
Marvell - Santa Clara, CA - US$100,840-151,000 per year
, Ethernet, and ARM CPU cores. What You Can Expect As a SoC-level design verification engineer, the candidate... will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. He...
April 12
PCIe Sub System Design Verification Engineer
Advanced Micro Devices - Santa Clara, CA
_ THE ROLE: AMD is looking for a Design Verification Engineer willing to take on the challenge of becoming part of the... PCIe Sub-System Design Verification team. In this role you will be given an opportunity to work on the next generation...
April 9
Design Verification Engineer, Senior Staff
Marvell - Santa Clara, CA - US$124,160-186,000 per year
standard tools and processes Develop constrained-random verification test environment using System Verilog, UVM and C... and other verification engineers to develop and implement verification test plans, schedules, and project deliverables. Manage, debug tests...
May 16
Design Verification Engineer, Principal
Marvell - Santa Clara, CA - US$137,510-206,000 per year
testbench components using SystemVerilog, UVM, C, and C++. Create comprehensive test plans based on architecture and design... design blocks. Investigate and debug test failures, identifying root causes related to both the test environment and the...
April 17
Principal Engineer - Design Verification
Marvell - Santa Clara, CA - US$137,510-206,000 per year
System Verilog/UVM/OVM. Strong experience with writing and executing detailed verification test-plan. Strong experience.... Strong experience with object-oriented design and implementation. Preferred/Plus: Hands-on verification experience with subsystems...
April 12