Staff, PHYSICAL DESIGN
onsemi
- Bangalore, Karnataka
- Permanent
- Full-time
- STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc…)
- Generating ECO for timing closure for complex multi power domain designs
- Good experience in running STA regression with high number of modes/corners efficiently.
- Power recovery with STA signoff
- Debug constraint issues in P&R environment
- LEC/Low power checks experience
- Strong in problem solving with deep understanding of technical issues.
- Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- BS in Electrical Engineering or related + 6 years of experience, or MS + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Solid track record of releasing complex ICs to market
- Ability to clearly articulate issues, challenges, and concerns to all levels of management
- Must have good written and verbal cross-functional communication skills
- BS in Electrical Engineering or related + 6 years of experience, or MS + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Solid track record of releasing complex ICs to market
- Ability to clearly articulate issues, challenges, and concerns to all levels of management
- Must have good written and verbal cross-functional communication skills