Hope you're doing well !! We are hiring for the Senior RTL/ Design Verification Design Engineer role. Please find the JD below JOB Designation: Senior RTL/ Design Verification Engineer JOB Location: Bangalore, Hyderabad, India Mode of Hiring: Full-time [FTE] Notice Period: Immediate to 60 days Experience:4 years Required Skills Good understanding of mixed signal concepts Good knowledge of RTL digital design fundamentals Deep knowledge of Verilog and System-Verilog Understanding of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Working knowledge of synthesis, static timing, DFT is a huge plus Good knowledge of System-Verilog assertions, checkers, scoreboard, and other design verification techniques Good knowledge of scripting languages. Perl and Python are plusses Good knowledge of Firmware, calibration, and adaptation Algorithm developments Strong communication and presentation skills and 3+ years of DDR/SERDES and supported protocols knowledge is a plus Expertise in multi protocols and PCS architecture such as PCIe, SATA, SAS, Ethernet Experience in PHY-level protocol test suite development and integration with link layer controllers is a plus Verilog-A/System Verilog, functional verification skills. Ability and desire to lead while providing technical guidance If anyone is interested, please send an updated CV to [HIDDEN TEXT]