Principal ASIC Design Engineer
Fortinet - Sunnyvale, CA
/FPGA design from specification to RTL implementation Perform ASIC/FPGA verification, lint/cdc, synthesis, timing analysis... Strong track record of ASIC/FPGA design from concept to mass production Hands on experience in Verilog HDL coding and verification...
February 27
Senior ASIC Design Engineer, Hardware Compute Group
Amazon - Sunnyvale, CA - $127,300 per year
methodologies and EDA tools - Experience working with Synthesis, timing and design constraints DESCRIPTION As a Sr. ASIC Design... this role you will: - Micro-architect and design hardware accelerator IP in Verilog HDL - Help define and own ASIC design...
April 9
Cellular ASIC Design Integration Engineer
Apple - Sunnyvale, CA
. This position requires thorough knowledge of the ASIC design flow, FE and design verification, synthesis, scripting and netlist... generation. Knowledge of ASIC/SoC design flow. Knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX...
April 11
Senior Principal ASIC Design Engineer
Fortinet - Sunnyvale, CA
Job Description: Job Description: As a key member of Fortinet's ASIC design team you will help design and architect... design & verification and lead low power design methodology. Candidate must be able to work with self-motivation and deliver...
March 12
Cellular SOC Design Verification Engineer
Apple - Sunnyvale, CA
protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc. As a Design Verification Engineer... on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting...
April 14