Talent Staffing Services - Santa Clara, CA
Design Verification Engineer Location: Santa Clara, CA Responsibilities: Architect and Create verification... of Register Transfer Level and Gate simulations and resolve them by working with design engineers. Create low power testcases...
May 21
iTech - Santa Clara, CA
Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great... and resolve them by working with design engineers. Create low power testcases using UPF or CPF to verify the desired power intent...
May 16
OmniVision - Santa Clara, CA - $126,984-130,000 per year
chip bring-up, validation, and debugging using FPGA and Python. Define the block level design document such as interface...Conduct image sensor array/analog related timing control design and Image Signal Processing (ISP) system level...
April 4
Sr. Staff ASIC Design Engineer
CyberCoders - Santa Clara, CA
and we are now looking for a senior/staff level ASIC Design Engineer to join us in our (HQ) Santa Clara location on a full time basis... and chip level. Participate in FPGA emulation and post-silicon validation. Write design specification Requirements: 10...
March 17
OmniVision - Santa Clara, CA - $110,600-135,000 per year
performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture...Minimum MSEE, or equivalent OR BSEE, or equivalent, plus 2 years of digital design experience Familiar with digital...
May 22