Principal Design Engineer – Memory Modeling Portfolio
Cadence Design Systems - Hsinchu City
. As a Principal Design Engineer you will be responsible for scheduling, designing, developing, and supporting IP models of system..., and supporting existing system level memory model products. Perform as individual contributor for RTL design, verification...
March 5
Principal Design Engineer – Memory Modeling Portfolio
Cadence Design Systems - Hsinchu City
. As a Principal Design Engineer you will be responsible for scheduling, designing, developing, and supporting IP models of system..., and supporting existing system level memory model products. Perform as individual contributor for RTL design, verification...
February 8
Principal Engineer, Mixed Signal Circuit Design
Infinera - Jhubei, Hsinchu County
The successful candidate shall lead the design efforts of high-speed low-noise clocking circuity, including the... by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient...
December 21
Cadence Design Systems - Hsinchu City
Jasper engineering team is seeking a Product Engineer to help drive the industry’s leading formal verification tool. The... Product Engineer (PE) bridges the gap between customers, R&D, and field Application Engineers (AEs). In this highly creative...
March 8
Cadence Design Systems - Hsinchu City
simulation. Understanding of analog/RF/mixed-signal IC design and verification practices is a strong plus. Candidate... design, and experience in relevant software frameworks is a plus. Exposure to high-performance numerical computing, CPU/GPU...
February 23